• Built to speed up the process of PowerDRC/LVS is to speed up the process of physical verification
  • Silicon-proven: 500nm, 350nm, 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
  • Effective at 32nm and 28nm
  • Fastest and most accurate native flat DRC engine in the market
  • Predictable performance and behavior
  • Multi-CPU and hierarchical operations for linear performance gain
  • Allows user to:
  • Adjust DRC and LVS run parameters
  • Save them in a run configuration file
  • Read a saved configuration
  • Run PowerDRC/LVS
  • View run progress
  • Review results
  • Debug violations, etc.

  • 7 efficient comparison algorithms applied automatically and dynamically
  • Silicon-proven: 250nm, 180nm, 130nm, 90nm, 65nm, 40nm
  • Predictable performance and behavior
  • Up to 10x speedup in extraction due to processing of array instances
  • Rich reporting including reports on multiple labels, floating labels, hier cells and open nets
  • Graphical debugging with PowerRDE and Short Finder utility
    XOR is a regular diffing function for two layouts. It involves profound comparison of corresponding layers in pairs according to rule file - either generated automatically or specifically written. In PowerDRC/LVS,
    XOR operation leverages multi-CPU and multi-core technologies for the best efficiency. It becomes truly impressive when XOR is combined with QuickDiff with manifold eventual speedup.
    QuickDiff is a quick check for small pre-tapeout changes (often called ECO - engineering change order) by means of special heuristic algorithms. It is intended primarily to detect differences (or ensure their absence) in two revisions of a given layout close before tapeout.
      PowerDRC/LVS allows for extraction of parasitic capacitances with high degree of accuracy.
      The supported input formats include GDS, OASIS or OpenAccess for layout, and CDL, SPICE, or VERILOG for schematic netlist.
      In PowerDRC/LVS one and the same engine is used to run DRC, LVS, and RCX, so to run parasitic extraction you may use either a dedicated rule deck or an extraction rule deck with RCX rules.
      PowerRCX results correlate with proven in silicon on the following processes:
      • IHP SG13S 130nm
      • IHP SGB25V 250nm
      • TSMC CL018 and 152G 180nm (with shrink 0.84)
      Running PowerDRC on a special fill rule deck results in generating of output.gds file with fill layers. The developer may attach these layers later as a separate group to some cell/top cell (hierarchically) using a layout editor.

      Fill operation creates layers filled with specified rectangles at certain distance with or without offsets, either inside or outside the layer. Filling also may be done with a cell that contains arbitrary shapes in several different layers.
      Short Finder is a special utility for graphical LVS debug purposes.
      It delivers the following functionality:
      • Suggests a short location
      • Shows shorted net polygons in a table format
      • Allows to assign label for selected a polygon
      • Allows to mark a polygon as 'deleted'
      • Recalculates the shortest path
      • Works interactively via KLayout editor